be used to provide a number of address
spaces. These address spaces may be used to provide degrees of isolation
between users. Such support can consist
of a completely different address space
for each user, thus providing complete
isolation, or a shared area may be
provided by mapping a portion of each
address space to a single common storage
area. Also, with DAS, instructions are provided which permit a semiprivileged
program to access more than one such
address space. Dynamic address trans­
lation with DAS provides for the
translation of virtual addresses from
two different address spaces without
requiring that the translation parame­
ters in the control registers be changed. These two address spaces are
called the primary address space and the
secondary address space.
In the process of replacing blocks of
main storage by new information from an external medium, it must be determined
which block to replace and whether the
block being replaced should be recorded
and preserved in auxiliary storage. To
aid in this decision process, a refer­
ence bit and a change bit are associated
with the storage key.
Dynamic address translation may be spec­
ified for instruction and data addresses
generated by the CPU but is not avail­ able for the addressing of data and of
CCWs and IDAWs in I/O operations. The
channel-indirect-data-addressing facili­
ty is provided to aid I/O operations in
a virtual-storage environment. The dynamic-address-translation facility
includes the instructions LOAD REAL
ADDRESS, RESET REFERENCE BIT, and PURGE TLB. It makes use of control register 1
and bits 8-12 in control register O. When DAS is installed, the dynamic­
address-translation facility also makes
use of control register 7.
The dynamic-address-translation facility
includes the handling of 2K-byte and
4K-byte pages and 64K-byte and 1M-byte
segments. On some models, the 2K-byte­ page size and 1M-byte-segment size may
not be offered.
Dynamic address translation is enhanced
by that part of the extended facility
that includes the instruction INVALIDATE PAGE TABLE ENTRY and the common-segment
facility. On some models, the common­
segment facility permits improvement of
TlB utilization by means of a common­
segment bit in the segment-table entry. On other models, this bit is ignored,
with no performance improvement.
Dynamic address translation is the proc­
ess of translating a virtual address
during a storage reference into the
corresponding real address. When OAT is
off, the logical address is treated as a real address. When DAS is not installed
and DAT is on, a logical address is
treated as a virtual address and is
translated during a storage reference
into the corresponding real address.
When DAS is installed and OAT is on, the
virtual address may be either a primary
virtual address or a secondary virtual
address. Primary virtual addresses are
translated by means of the primary
segment-table designation and secondary
virtual addresses by means of the
secondary segment-table designation.
After selection of the appropriate
segment-table designation, the trans­
lation process is the same for both
types of virtual address.
In the process of translation, two units
of information are recognized --seg­
ments and pages. A segment is a block
of sequential virtual addresses spanning
65,536 (64K) or 1,048,576 (1M) bytes and
beginning at an address that is a multi­
ple of its size. A page is a block of
sequential virtual addresses spanning 2,048 (2K) or 4,096 (4K) bytes and
beginning at an address that is a multi­
ple of its size. The size of the
segment and page is controlled by bits
8-12 in control register o.
The virtual address, accordingly, is
divided into a segment-index (SX) field, a page-index (PX) field, and a byte­
index (BX) field. The size of these
fields depends on the segment and page size. The segment index starts with bit 8 of
the virtual address and extends through
bit 15 for a 64K-byte segment size and
through bit 11 for a 1M-byte segment
size. The page index starts with the
bit following the segment index and
extends through bit 19 for a 4K-byte
page size and through bit 20 for a
2K-byte page size. The byte index
consists of the remalnlng 11 or 12
rightmost bits of the virtual address. The virtual address has the following
format:
For 64K-byte segments and 4K-byte pages: 1////////1 SX I PX I BX 0 8 16 20 31
For 64K-byte segments and 2K-byte pages: 1////////1 SX I PX BX 0 8 16 21 31
For 1M-byte segments and 4K-byte pages: 1////////1 SX PX BX 0 8 12 20 31
Chapter 3. Storage 3-21

For 1M-byte segments and 2K-byte pages: 1////////1 SX PX BX
o 8 12 21 31 Virtual addresses are translated into
real addresses by means of two trans­
lation tables: a segment table and a
page table. These reflect the current
assignment of real storage. The assign­
ment of real storage occurs in units of
pages, the real locations being assigned
contiguously within a page. The pages
need not be adjacent in real storage
even though assigned to a set of sequen­
tial virtual addresses.
TRANSLATION CONTROL
Address translation is controlled by the
OAT-mode bit in the EC-mode PSW and by a
set of bits, referred to as the trans­
lation parameters, in control registers
o and 1. When DAS is installed, an
additional bit in the EC-mode PSW is
included, and control register 7 is
included as part of the translation
parameters. Additional controls are
located in the translation tables.
Translation Modes
When the
facility is
dynamic-address-translation
installed without DAS, the
3-22 System/370 Principles of Operation CPU can operate with OAT either on or
off. The mode of operation ;s
controlled by bit 5 of the EC-mode PSW, the OAT-mode bit. When this bit is one, OAT is on, and logical addresses are
treated as virtual addresses; when this
bit is zero or the BC mode is specified, OAT is off, and logical addresses are
treated as real addresses.
When DAS is installed, two bits in the
EC-mode PSW control dynamic address
translation: bit 5, the OAT-mode bit,
and bit 16, the address-space-control
bit. When aBC-mode PSW is specified, or, when in an EC-mode PSW the OAT-mode
bit is zero, OAT is off, the CPU is said
to be in the real mode, and instruction
and logical addresses are treated as
real addresses. When, in an EC-mode PSW, the OAT-mode bit is one (OAT is on)
and the address-space-control bit is zero, the CPU is said to be in the
primary-space mode, and instruction and
logical addresses are treated as primary
virtual addresses. When, in an EC-mode PSW, OAT is on and the address-space­
control bit is one, the CPU is said to
be in the secondary-space mode, and
logical addresses are treated as second­
ary virtual addresses. The various
modes are shown in the figures "Trans­
lation Modes without DAS" and
"Translation Modes with DAS."