Handling of Addresses PSW Bit
logical Instruction
5 112 OAT Mode Addresses Addresses
- 0 Off Real mode (Be mode) Real Real 0 1 Off Real mode Real Real
1 1 On Primary-space mode Primary Primary Translation Modes without DAS PSW Bit
5 112 1
16 OAT Mode
- 0 - Off Real mode (BC mode) 0 1 - Off Real mode
1 1 0 On Primary-space mode
1 1 1 On Secondary-space mode
Translation Modes with OAS Note: When the CPU is in the
secondary-space mode, it is unpredict­
able whether instruction addresses are treated as primary virtual or secondary
virtual addresses. However, all copies
of an instruction used in a single
execution are fetched from a single
space, and the machine can change the
interpretation of instruction addresses
as primary virtual or secondary virtual
only between instructions and only by
performing a checkpoint-synchronizing
function. Programming Notes
1. Predictable program is
ensured in the secondary-space mode
only when the instructions are
fetched from virtual-address
locations which translate to the same real address by means of both
the primary and secondary segment
tables. Thus, a program should not
enter the secondary-space mode
unless the aforementioned condi­
tions exist.
2. The requirement limiting when the CPU can change the address space
used for fetching instructions
eliminates problems with CPU retry, OAT pretesting, and trial execution
of instructions for the purposes of
determining PER events.
virtual virtual
Handling of Addresses
logical Instruction
Addresses Addresses
Real Real Real Real Primary Primary virtual virtual
Secondary See note
virtual Control Register Q When OAS is not installed, five bits are provided in control register 0 which are
used In controlling dynamic address
translation. When DAS is installed, a sixth bit is provided. The bits are
assigned as follows: 101 TF
5 8 13
Secondary-Space Control (D): Bit 5 of
control register 0 is the secondary­
space-control bit. This bit is provided
as part of OAS. When this bit is zero and execution of MOVE TO PRIMARY, MOVE TO SECONDARY, or SET ADDRESS SPACE CONTROL is attempted, a special­
operation exception is recognized. When
this bit is one, it indicates that the
secondary segment table is attached when
the CPU is in the primary-space mode.
Translation Format eTF): Bits 8-12 of
control register 0 are-called the trans­
lation format, which controls the page
size and segment size. Some models do
not implement all four of the combina­
tions, as shown in the following table. Chapter 3. Storage 3-23

Bits of Control Register 0 Page Segment 81 9110111112 Size Size Provided (Bytes) (Bytes) 0 1 0 0 0 opt 2K 64K 0 1 0 1 0 opt 2K 1M
1 0 0 0 0 Std 4K 64K
1 0 0 1 0 Opt 4K 1M
All others Inv
Explanation: Opt Std
Inv Optional. The code is invalid
on some models, even though the translation facility is installed.
Standard. The code is valid on all models with the trans­
lation facility installed.
Invalid. The code is not valid
on any model.
Translation Format
When an invalid bit combination is detected in bit positions 8-12, a
translation-specification exception is
recognized as part of the execution of
an instruction using address transla­
tion.
Control Register 1
Control register 1 contains the primary
segment-table designation (PSTD). The
register has the following format:
PSTL I Primary Segment- _ Table Origin o 8 26 31
Primary Segment-Table length (PSTl): Bits 0-7 of control register 1 specify
the length of the primary segment table in units of 64 bytes, thus making the
length of the segment table variable in multiples of 16 entries. The length of
the primary segment table, in units of
64 bytes, is one more than the PSTL
value. The contents of the length field are used to establish whether the entry
designated by the segment-index portion
of a primary virtual address falls with­
in the primary segment table. Without
DAS, this field is sometimes referred to as the segment-table length.
3-24 System/370 Principles of Operation Primary Segment-Table Origin (PSTO): Bits 8-25 of control register 1,--wTth six zeros appended on the right, form a
24-bit real address that designates the
beginning of the primary segment table.
Without DAS, this field is sometimes
referred to as the segment-table origin.
With extended real addressing, the
primary segment-table origin is still a 24-bit real address and extended on the left with zeros. Space-Switch-Event-Control Bit When bit 31 of control register 1 is one
and execution of PROGRAM CALL with space switching (PC-55) or PROGRAM TRANSFER
with space switching (PT-ss) is
completed, a space-switch-event program
interruption occurs. The space-switch­
event-control bit is also examined by LOAD ADDRESS SPACE PARAMETERS, and, if
it is one, condition code 3 is set. When DAS is not installed, this bit is
ignored.
Bits 26-30 of control register 1 are not assigned and are ignored. Control Register I
When DAS is installed, control register
7 contains the secondary segment-table
designation (SSTD). The register has the following format:
o
Secondary Segment­ Table Origin 8 26 31
Secondary Segment-Table Length (SSTl):
Bits 0-7 of control register 7 specify
the length of the secondary segment table in units of 64 bytes, thus making the length of the segment table variable in multiples of 16 entries. The length
of the secondary segment table, in units
of 64 bytes, is one more than the SSTL
value. The contents of the length field are used to establish whether the entry
designated by the segment-index portion
of a secondary virtual address falls
within the secondary segment table.
Secondary Segment-Table Origin (SSTO): Bits 8-25 of control register 7, with
six zeros appended on the right, form a
24-bit real address that designates the
beginning of the secondary segment
table. With extended real addressing, the secondary segment-table origin is
still a 24-bit real address and is extended on the left with zeros.
Bits 26-31 of control register 7 are not
assigned and are ignored.