LOAD ADDRESS SPACE PARAMETERS
(LASP) MOVE TO PRIMARY CMVCP) MOVE TO SECONDARY CMVCS) MOVE WITH KEY (MVKC) PROGRAM CALL (PC) PROGRAM TRANSFER CPT) SET ADDRESS SPACE CONTROL (SAC) SET SECONDARY ASN (SSAR)
8. Nine new exception or event condi­
tions which result in a program
interruption. These conditions
are:
AFX-translation exception
ASN-translation-specification
exception
ASX-translation exception
EX-translation exception
LX-translation exception
PC-translation-specification excep-
tion
Primary-authority exception
Secondary-authority exception
Space-switch event
For page-and segment-translation
exceptions, a bit is stored with
the translation-exception address.
This bit indicates whether the
address was translated by using the
primary or secondary segment-table
designation.
The following System/370 instructions
are changed or affected by the installa­
tion of DAS, as noted: • • • Execution of the SET PSW KEY FROM ADDRESS instruction is permitted in
the problem state, subject to the
contents of bit positions 0-15 of
control register 3. When the bit
in the control register correspond­
ing to the PSW-key value to be set
is one, execution is allowed;
otherwise, a privileged-operation
exception 1S recognized. The
contents of control register 3 are
ignored in the supervisor state.
Execution of the INSERT PSW KEY instruction is permitted in the
problem state, subject to the
extraction-authority control, bit 4
of control register O. When the
bit is one, execution is allowed;
otherwise, a privileged-operation
exception is recognized. The
extraction-authority control is
ignored in the supervisor state. LOAD REAL ADDRESS uses the contents
of control register 7, instead of
the contents of control register 1,
when PSW bit 16 is one. Thus the
second operand is translated either
as a primary virtual address or as
a secondary virtual address,
depending on the mode specified in
the PSW. • The second-operand address of EXECUTE is defined to be an
instruction address rather than a
logical address. In secondary­
space mode, it is thus unpredict­
able whether the target instruction
is fetched from the primary space
or the secondary space.
EXTENDED
Includes the instructions INVALIDATE PAGE TABLE ENTRY and TEST PROTECTION, the common-segment facility and the
associated bit position in the segment­
table entry, low-address protection and
the associated control-register position
for the low-address-protection control
bit, and 12 MVS-dependent instructions. INVALIDATE PAGE TABLE ENTRY lncludes
revisions to the READ DIRECT and WRITE DIRECT instructions to make the operand
addresses real instead of logical. EXTENDED-PRECISION FLOATING POINT Includes the extended-precision
floating-point instructions (listed in
Appendix B).
EXTENDED REAL ADDRESSING Provides for a 26-bit page-frame real
address in the page-table entry for
4K-byte pages.
EXTERNAL SIGNALS
to external
signals, the
Includes the extension
interruptions for external
control-register position
external-signal mask, and the
accept external signals.
FAST RELEASE
for the
means to Provides the start-I/O-fast-release (SIOF) function on the channel when the
START I/O FAST RELEASE instruction is
executed. This function provides for
fast release of the CPU, which occurs
before the device-selection procedure is
completed, reducing the CPU delay asso­
ciated with the initiation of the I/O operation. When the SIOF function is
not implemented, START I/O FAST RELEASE
is executed as START I/O. Appendix D. Facilities D-3

FLOATING POINT Includes the floating-point instructions
(listed in Appendix B) and the
floating-point registers. The
floating-point facility, together with
the commercial instruction set, is some­
times referred to as the universal
instruction set.
HALT DEVICE
Provides the halt-device (HDV) function
on a channel when the HALT DEVICE
instruction is executed. When the HDV
function is not implemented, HALT DEVICE
is executed as HALT I/O. I/O EXTENDED LOGOUT Provides for the storing of detailed
channel-error information in a storage
area designated by a pointer.
LIMITED CHANNEL LOGOUT Provides four bytes of channel-status
information for model-independent recov­
ery from channel errors. MOVE INVERSE Includes the MOVE INVERSE instruction.
MULTIPROCESSING
Includes the following facilities, which
permit the formation of a multiprocess­
ing configuration: • Shared Main Storage • Prefixing • CPU-Address Identification • CPU Signaling and Response • TOO-Clock Synchronization
These facilities include four extensions
to the external interruption (external
call, emergency signal, TOD-clock-sync
check, and malfunction alert), control­
register positions for the TOD-clock­
sync-control bit and for the masks for
the four external-interruption condi­
tions, and the instructions SET PREFIX, 0-4 System/370 Principles of Operation
SIGNAL PROCESSOR, STORE CPU ADDRESS, and STORE PREFIX. PSW-KEY HANDLING
Includes the instructions SET PSW KEY FROM ADDRESS and INSERT PSW KEY. RECOVERY EXTENSIONS
Includes the following: • Machine-check external-damage code
at real locations 244-247, the
external-damage-code-validity bit
(bit 26 of the machine-check­
interruption code), and the
channel-not-operational indication
in the machine-check external­
damage code. • • The clear-channel (CLRCH) function
in a channel when the CLEAR CHANNEL
instruction is executed; when the
CLRCH function is not implemented,
CLEAR CHANNEL is executed as TEST
CHANNEL.
The full-channel-logout-valid bit
(bit 15) and the interface­
inoperative bit (bit 27) in the
limited channel logout.
SEGMENT PROTECTION Provides a segment-protection bit in the
segment-table entry. When the bit is
one, an attempt to store in the segment
causes a protection exception to be
recognized.
SERVICE SIGNAL
Provides an external interruption which
is used by the service-call logical
processor (SCLP) to signal to the
control program.
START-I/O-FAST QUEUING
Provides for fast release of the CPU by
the channel during the execution of
START I/O FAST RELEASE and the queuing
of the operation at the subchannel when
the control unit or device is busy,
rather than termination of the operation
by means of an I/O interruption with a deferred-condition-code-l indication.
The queuing of the operation at the