, Contents of Trace Entry for: Positions within Trace Entry PROGRAM CALL PROGRAM TRAHSFER SET SECOHDARY ASH Bytes 0-1 Hew PSW, bytes 0-1 Hew PSW, bytes 0-1 Uew PSW, bytes 0-1 Byte 2 Hex 90
1
Hex AOl Hex BOl Bytes 3-7 New PSW, bytes 3-7 New PSW, bytes 3-7 New PSW, bytes 3-7
Bytes 8-9 New PASH Hew PASH PASH Bytes 10-11 Hew SASN 0 New SASH Bytes 12-13 GR14 Old PASH 0 Bytes 14-15 After 0 Old SASH Bytes 16-19 0 0 0 Byte Bits 0-1 ILC2 ILC2 ILC2 20 Bits 2-3 CC CC CC Bits 4-7 PM PM PM Byte 21 CPU identity 3 CPU identity 3 CPU identity 3
Bytes 22-23 0 0 0 Bytes 24-27 PC number
4 0 0 28-31 TOO clock, TOO clock, TOO clock,
bytes 3-6 bytes 3-6 bytes 3-6
EXElanation:
1 Byte 2 contains the entry-type identifier value. This position is used to uniquely identify the type of event for which the entry is made. 2 Byte 20 contains the instruction-length code (ILC), condition code (CC) ,
and program mask ( pr·D of the old PSL.J . The ILC is alw<:lYs 2. 3 Byte 21, "CPU identity," is fetched from logical location 795.
4
Bytes 24-27 for PROGRAM CALL contain eight zero bits appended to the left
of the 24-bit effective address specified by the PROGRAM CALL instruction. The rightmost 20 bits constitute the PC number.
Trace-Entry Formats PROGRAM-EVENT RECORDING The program-event-recording (PER) facil­ ity is provided to assist in debugging progr<:lms. It permits the program to be alerted to the following types of events: Execution of a successful branch
instruction. Fetching of an instruction from the designated storage area. Alteration of the contents of the deslgn<:lted storag2 areu. Alteration of the contents of designated general reglsters. The program can selectively specify that
one or more of the above types of be recognized. The information concern­
ing a PER event is provided to the
program by means of a program inter­
ruption, with the cause of the
interruption being identified in the
interruption code. PER is onlyavail­
able in the EC mode. CONTROL-REGISTER ALLOCATION The information for controlling PER resides in control registers 9, 10, and
11 and has the following format: Chapter 4. Control 4-15
Control Register 9
EM IGen.-Re g Masks
o 4 16 31
Control Register 10 Starting Address
o 8 31
Control Register 11
Ending Address
o 8 31 PER-Event Masks (EM): Bits 0-3 of
control register 95pecify which types
of events are recognized. The bits are assigned as follows:
Bit 0: Bit 1:
Bit 2: Bit 3:
Successful-branching event Instruction-fetching event Storage-alteration eV2nt General-register-alteration
event Bits 0-3, when ones,
corresponding types of nized. When a bit is sponding type of recognized. specify that the events be recog­
zero, the corre-
event ; s not PER yp.neral-Regi ster l"1asks: Bi ts 16-31
of control register 9 specify which general registers are designated for recognition of the alteration of their contents. The 16 bits, in the sequence of bit numbers, correspond one for one with the 16 registers, in the sequence of ascending register WhQn a bit is one, the illteration of the associated register is recognized; when it is zero, the alteration of the regis­ ter 1S not recognized. PER Starting Address: Bits 8-31 of
control register 10 are the address of the beginning of the designated storage area. Ending Address: Bits 8-31 of
control register 11 are the address of the end of the designated storage area. 1. Models may operate at reduced performance while the CPU 1S enabled for PER events. In order to ensure that CPU performance is not degraded because of the opera­ tion of the PER facility, programs
4-16 System/370 Principles of Operation that do not use it should disable
the CPU for PER events by setting
the PER mask in the EC-mode PSW to
zero. No degradation due to PER occurs in the BC mode or when the PER mask in the EC-mode PSW is zero. Disabling of the CPU for PER events in the EC mode by means of
the masks in control register 9
does not necessarily prevent
performance degradation due to the facility. 2. Some degradation may be experienced
on some models every time control
registers 9, 10, and 11 are loaded,
even when the CPU is disabled for PER events (see the programming
note under "Storage-Area Desig­ nation"). OPERATION PER is under control of bit 1 of the
EC-mode PSW, the PER mask. When the PER mask, a particular PER-event mask bit, and, for general-register-alteration
events, a particular general-register mask bi t are all ones, the CPU is enabled for the corresponding type of
event; otherwise, it is disabled. In
the BC mode, the CPU is disabled for PER events. An interruption due to a PER event
normally occurs after the execution of
the instruction responsible for the
event. The occurrence of the event does
not affect the execution of the instruc­ tion, which may be either completed,
partially completed, terminated,
suppressed, or nullified. When the CPU is disabled for a partic­ ular PER event at the it occurs,
either by the PER mask in the PSW or by the masks in control register 9, the event is not recognized.
A change to the PER mask in the PSW or
to the PER control fields in control registers 9, 10, and 11 affects PER starting with the execution of the imme­ diately following instruction. If a PER event occurs during the execution of an instruction which changes the CPU from being enabled to being disabled for that
type of event, that PER event is recog­ nized. PER events may be recognized in a trial execution of an instruction, and subse­
quently the instruction, DAT-table entries, and operands may be refetched
for the actual execution. If any
refetched field was modified by another CPU or by a channel between the trial execution and the actual execution, it is unpredictable whether the PER events indicated are for the trial or the actu­ al execution.
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